The invention relates to a circuit arrangement for the conversion of analog signals into binary signals wherein rectangular signals are generated from the analog signals and edges of the rectangular signals are allocated to zero axis crossings of the analog signals.
In numerous signal processing units, particularly for a magnetic or optical recording of data on a recording medium, analog signals are converted into corresponding binary signals which are respectively allocated to a change of status of the recording medium.
It would be conceivable to first limit the analog signals and to amplify them for the conversion of these analog signals into binary signals. In case read output signals of magnetic recording media are provided as analog signals, the read output signals generated by the read head are usually differentiated after a pre-amplification in order to allocate the maximum values and minimum values of the read output signals to zero axis crossings of the differentiated read output signals, which shall be referred to in the following as analog signals. As already mentioned, these analog signals are then converted into corresponding rectangular signals by amplification and limitation. Pulses are generated at every change of the binary values of the rectangular signals, these pulses driving a one-shot multivibrator whose delay time corresponds to about half the shortest period duration of the analog signals or of the rectangular signals. After the delay time, the respective binary values of the rectangular signals are interrogated and a binary signal is generated at every change of the binary values of the rectangular signals.
The one-shot multi-vibrator serves a time-domain filter, predominantly for eliminating brief-duration disturbances of the analog signals and thus of the rectangular signals as well. In case, however, disturbances are contained in the analog signals or rectangular signals after the expiration of the delay time, these can lead to faulty binary signals.